1. Field of the Invention
The present invention relates to an Analog to Digital Converter (ADC), and more particularly, to a digital background calibration method and apparatus for calibrating a difference attributable to a capacitor mismatch in a Digital to Analog Converter (DAC).
2. Description of the Related Art
In general, an ADC is a circuit for converting an analog signal into a digital signal and is one of core blocks that are necessary in all the signal processing fields as well as in the wireless communication field.
In particular, in the case of application fields, such as portable devices and wireless sensor networks in which a battery is used as a power supply source and thus available energy is very limited, it is necessary to minimize power consumption by lowering a supply voltage.
An ADC that is most advantageous in minimizing power consumption is advantageous in term of low power because it does not consume great power because of its Successive Approximation Register (SAR) structure, but is disadvantageous in that it uses a larger capacitor than that of other ADCs.
In general, in order to increase resolution of 1 bit, capacitance of a twice large capacitor is necessary. If the size of a capacitor is increased, an area occupied by the capacitor is increased and power consumption is also increased. Furthermore, there is a problem in that accuracy in converting an analog value into digital code is lowered because the degree of a capacitor mismatch is increased.
FIG. 1 is a detailed diagram showing the structure of a conventional fully differential Successive Approximation Register ADC (SAR-ADC) 100. The SAR-ADC 100 includes the conventional fully differential a Digital to Analog Converter (DAC) 110 configured to have a differential structure, a comparator 130 configured to compare a first output signal 111 and a second output signal 112, that is, voltages output from the DAC, with each other, and a Successive Approximation Register (SAR) 130.
The operation of the conventional fully differential Successive Approximation Register ADC (SAR-ADC) 100 is described below with reference to FIG. 1.
First, the conventional fully differential DAC 110 converts a digital signal into an analog voltage and outputs the analog voltage. The comparator 120 compares the sizes of the first output signal 111 and the second output signal 112 that are the output voltages of the conventional fully differential DAC 110. The comparator 120 outputs information, indicating which one of the two values is greater as a result of the comparison, as one digital value. Thereafter, the final digital result is obtained through the SAR 130.
Here, an interested point is the conventional fully differential DAC 110.
FIG. 2 is a circuit diagram showing the binary-weighted capacitor array of the conventional fully differential DAC 110.
In general, the conventional fully differential DAC 110 has a binary-weighted structure, such as that shown in FIG. 2. The binary-weighted structure refers to a structure in which the capacitor array of a DAC is increased twice toward upper bits. Assuming that capacitance of a capacitor having the lowest digital code is unit capacitance of 1, capacitance of the capacitor is increased to double toward upper digital code. A binary search is performed for an efficient comparison. In this structure, it may be said that the most important thing is that a ratio of adjacent capacitors is 2.
A total amount of capacitance of capacitors that are connected in parallel is equal to the sum of the capacitors. A capacitor value of an upper bit that has the greatest influence on the performance of an ADC is divided using such as advantage. Since the capacitor value is divided by half in the binary-weighted structure, it becomes equal to capacitance of the capacitor of a lower bit thereof.
When the number of bits ‘n’ of digital code is small, the degree of a capacitor mismatch does not have a great influence on a result because it is relatively smaller than a value that corresponding to the Least Significant Bit (LSB). If the number of bits is increased, however, a mismatch may be increased to several times the LSB because a capacitor value is increased.
Such a capacitor mismatch has a great influence on Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) as well as the Effective Number Of bits (SNOB) that is an important criterion indicative of the performance of an ADC, thereby making it difficult to fabricate a low-power high-resolution ADC.